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This paper presents a PIM-based (Processing-in-Memory) architecture based on new reconfigurable cell data path. The architecture delivers increased power/throughput/area efficiency compared to previous well-known architectures. The investigation of the new reconfigurable cell design was performed in 0.18 and 0.13 micron CMOS technology nodes. Specifications of individual blocks are presented as well as a comparison with existing designs for 8x8 2D DCT application.
SOC Conference, 2008 IEEE International
Date of Conference: 17-20 Sept. 2008