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Power/throughput/area efficient PIM-based reconfigurable array for parallel processing

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4 Author(s)
Purohit, S. ; Dept. of Electr. & Comput. Eng, Univ. of Massachusetts Lowell, Lowell, MA ; Chalamalasetti, S. ; Margala, M. ; Corsonello, P.

This paper presents a PIM-based (Processing-in-Memory) architecture based on new reconfigurable cell data path. The architecture delivers increased power/throughput/area efficiency compared to previous well-known architectures. The investigation of the new reconfigurable cell design was performed in 0.18 and 0.13 micron CMOS technology nodes. Specifications of individual blocks are presented as well as a comparison with existing designs for 8x8 2D DCT application.

Published in:
SOC Conference, 2008 IEEE International

Date of Conference: 17-20 Sept. 2008

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