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Energy consumption reduction mechanism by tuning cache configuration usign NIOS II processor

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2 Author(s)
Silva-Filho, A.G. ; Dept. of Comput. & Syst., Univ. of Pernambuco (POLI-UPE), Recife ; Lima, S.M.L.

The memory hierarchy of an embedded system can consume up to 50% of microprocessor system power (Segars, S.,2001). This paper proposes: (i) a design flow to estimate energy consumption and performance using an SoC system based on FPGA, and (ii) an automated architecture exploration mechanism based on parameter variation of a memory hierarchy and NIOS II processor. Results based on Mibench and XiRisc suite have demonstrated that, on average, with 9% of the design space, an energy consumption reduction of about 27% has been achieved, as well as an increase of 10% in the performance of the application.

Published in:

SOC Conference, 2008 IEEE International

Date of Conference:

17-20 Sept. 2008