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A new domain-specific reconfigurable sub-pixel interpolation architecture for multi-standard video motion estimation (ME) is presented. The mixed use of parallel and serial-input FIR filters achieves high throughput rate and efficient silicon utilisation. Flexibility has been achieved by using a multiplexed reconfigurable data-path controlled by a selection signal. Silicon design studies show that this can be implemented using 34.8 K gates with area and performance that compares very favourably with existing fixed solutions based solely on the H.264 standard.
SOC Conference, 2008 IEEE International
Date of Conference: 17-20 Sept. 2008