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Reducing power consumption is one of the important design goals for circuit designers. Power optimization techniques for bulk CMOS-based circuit designs have been extensively studied. As technology scales, FinFET has been proposed as an alternative for bulk CMOS when technology scales beyond 32 nm technology (E.J. Nowak et al., 2004). In this paper, we propose a power optimization framework for FinFET based circuit design, based on genetic algorithms. We exploit the unique feature of independent gate (IG) controls for FinFET devices to reduce the power consumption, and combine with other low power techniques such as multi-Vdd and gate sizing to achieve power optimization for FinFET-based circuits. We use 32 nm PTM FinFET device model (W. Zhao and Y. Cao, 2006) and conduct experiments on ISCAS benchmarks. The experimental results show that our methodology can achieve over 80% power reduction while satisfying the same performance constraints, comparing to the case that all the FinFET transistors are tuned to be the fastest ones.
SOC Conference, 2008 IEEE International
Date of Conference: 17-20 Sept. 2008