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A low power 32 nanometer CMOS digitally controlled oscillator

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2 Author(s)
Jun Zhao ; Northeastern University, Boston, MA, USA ; Yong-bin Kim

In this paper, a low power and low jitter 12-bit CMOS digitally controlled oscillator (DCO) design is presented. The CMOS DCO design is based on a ring oscillator implemented with Schmitt trigger based inverters. Simulations of the proposed DCO using 32 nm predictive transistor model (PTM) achieve controllable frequency range of around 570 MHz~850 MHz with a wide range of linearity. Monte Carlo simulation demonstrates that the time-period jitter due to random power supply fluctuation is under 75 ps and the power consumption is 2.3 mW at 800 MHz and 0.9 power supply.

Published in:

2008 IEEE International SOC Conference

Date of Conference:

17-20 Sept. 2008