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A systematic approach to synthesis of verification test-suites for modular SoC designs

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3 Author(s)
Surendran, S. ; Camera Phone Bus. Unit, Texas Instrum. India Ltd., Bangalore ; Parekhji, R. ; Govindarajan, R.

Verification is one of the important stages in designing an SoC (system on chips) that consumes upto 70% of the design time. In this work, we present a methodology to automatically generate verification test-cases to verify a class of SoCs and also enable re-use of verification resources created from one SoC to another. A prototype implementation for generating the test-cases is also presented.

Published in:

SOC Conference, 2008 IEEE International

Date of Conference:

17-20 Sept. 2008