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This paper presents a novel high-speed behavioural simulator (software-based emulator) for reconfigurable instruction cell based processors. These architectures are particularly suited to providing low-power, low-cost implementations of applications in a streaming environment, such as image signal processing, video playback, or base-band signal processing. As a result, many realistic applications operate on very large data sets, so simulation time plays a key role in the time to market. The key aspect of this work is an efficient serialisation algorithm (based on topological sort), able to capture the intricacies of reconfigurable processors that can be reconfigured very rapidly (ns). This allows for a new generation of high-speed emulation models to be constructed. The performance of this algorithm deployed in an interpreter-based model is compared to other simulation techniques. The emulator can achieve performance around two orders of magnitude higher than current event-driven software models, and similar to that of an FPGA-based model. This brings the simulation times low enough to be able to use this technology as the basis for feedback-directed optimisation, which can significantly improve the performance of application code.
SOC Conference, 2008 IEEE International
Date of Conference: 17-20 Sept. 2008