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The impact of process variations on circuit timing increases rapidly as technology scales. Consequently, it is important to consider timing variations at the early stages of circuit designs. Conventional high level synthesis relies on the worst-case delay analysis to guide the design space exploration, however, such worst-case timing analysis can results in overly conservative designs with pessimistic performance estimation. This paper presents a 0-1 integer linear programming (ILP) formulation that aims at reducing the impact of timing variations in high-level synthesis, by integrating overall timing yield constraints into scheduling and resource binding. The proposed approach focuses on how to achieve the maximum performance (minimum latency) under given timing yield constraints with affordable computation time. Experiment results show that significant latency reduction is achieved under different timing yield constraints, compared to traditional worst-case based approach.