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The role of interconnects in the performance scalability of multicore architectures

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2 Author(s)
Jiangjiang Liu ; Dept. of Comput. Sci., Lamar Univ., Beaumont, TX ; Mahapatra, N.R.

In this paper, we investigate how the interconnects used for instruction and data communication between the cores and the memory system limit multi-core chip performance scalability. We show the extent to which this limitation can be alleviated by: (1) using a simple thread scheduling approach that balances memory access demands across cores, (2) using techniques (such as compression) that improve effective interconnect bandwidth, and (3) a combination of the two. We find that, across a range of SPEC CINT2000 programs, the first approach improves multi-core chip performance by 14.99%-33.31%, the second approach by 22.28%-64.43%, and the third by 33.97%-87.92%.

Published in:

SOC Conference, 2008 IEEE International

Date of Conference:

17-20 Sept. 2008