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VEST - An intelligent tool for timing SoCs verification using UML timing diagrams

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2 Author(s)
Andrzej Pulka ; Institute of Electronics, Silesian University of Technology, Gliwice, Poland ; Adam Milik

The paper concerns problems of the formal verification of timings in complex electronic devices - systems on chip (SoC). The authors discuss various approaches to complex systems verification. The formal procedures for systems timings checking are presented. The models are defined as models of computation in the heterogeneous (HDL/SystemC/MATLAB) environment. The verification process is performed on intermediate UML descriptions. The methodology makes use of timing diagrams introduced to UML 2.x standard. The entire system works under VEST (verification expert system tool) implemented in PROLOG. Some experiments and results concerning communication within AMBA-bus based platform are considered.

Published in:

Specification, Verification and Design Languages, 2008. FDL 2008. Forum on

Date of Conference:

23-25 Sept. 2008