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The Design of Bi-CMOS LVDS Output Buffer with ESD Protection Circuit Using 90nm CMOS Technology

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5 Author(s)
Yongseo Koo ; Dept. of Electron. Eng., Seokyeong Univ., Seoul ; Kwangyeob Lee ; Jaechang Kwack ; Jongil Won
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This paper presents the design of novel LVDS (Low-Voltage-Differential-Signaling) output buffer for Gb/sper-pin operation using 90 nm CMOS technology. The proposed LVDS driver is designed to reduce chip area, using a novel bipolar transistor switch. The proposed LVDS transmitter is operated at 1.8 V low-power supply. Its maximum data rate is 2.8 Gb/s approximately. Also, the new structural ESD (Electro-Static Discharge) protection device is designed to improve the proposed LVDS driver's ESD protection performance. The proposed device can reduce latch-up phenomenon in normal operating condition. In the measurement result, the proposed ESD clamp has trigger voltage of 3.7 V and holding voltage of 2.3 V. The robustness of the LVDS driver with proposed ESD protection has measured to about 2kV (IEC61000-4-2).

Published in:

Advances in Electronics and Micro-electronics, 2008. ENICS '08. International Conference on

Date of Conference:

Sept. 29 2008-Oct. 4 2008