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Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors

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5 Author(s)
Metra, C. ; DEIS, Univ. of Bologna, Bologna ; Omana, M. ; Mak, T.M. ; Rahman, A.
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In this paper we present an on-chip clock jitter digital measurement scheme for high performance microprocessors. The scheme enables in-situ jitter measurement of the clock distribution network during the test or the debug phase. It provides very high measurement resolution, despite the possible presence of power supply noise (constituting a major cause of clock jitter) affecting itself. The resolution is higher than a min sized inverter input-output delay, and can on principle be further increased, at some additional costs in terms of area overhead and power consumption. In this paper, a resolution of the 1.8% of the clock period is achieved with limited area and power costs.

Published in:

Defect and Fault Tolerance of VLSI Systems, 2008. DFTVS '08. IEEE International Symposium on

Date of Conference:

1-3 Oct. 2008