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Analyzing the Impact of Fault-tolerant BIST for VLSI Design

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3 Author(s)
Daasch, W.R. ; Dept. of Electr. & Comput. Eng., Portland State Univ., Portland, OR ; Jain, S. ; Armbrust, D.

This paper examines fault-tolerant DfT (Design for Test) circuits as an effective approach for improved reliability and lower defective parts per million (DPPM). The paper provides a comprehensive examination of one alternative, quadded gate, inter-leaved node logic design. Quadded DfT circuitry is compared to circuitry with no fault tolerance in terms of area, power and performance. Ever shrinking device sizes are challenging the reliability limits and testing capabilities of a modern day integrated circuit (IC). Parametric variations, higher gate counts and lower pin counts render fault avoidance techniques ineffective and make fault detection an engineering challenge. Higher defect rates and Ultra Large Scale Integration (ULSI) will require bigger and complex DfT circuitry. This will result in more chips being rejected due to DfT failures. Fault-tolerant DfT directly translates to shorter time-to-market, increased reliability and improved yield learning.

Published in:

Defect and Fault Tolerance of VLSI Systems, 2008. DFTVS '08. IEEE International Symposium on

Date of Conference:

1-3 Oct. 2008