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A 622-Mb/s Mixed-Mode BPSK Demodulator Using a Half-Rate Bang-Bang Phase Detector

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5 Author(s)
Duho Kim ; Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul ; Kwang-Chun Choi ; Young-Kwang Seo ; Hyunchin Kim
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A new mixed-mode binary phase shift keying (BPSK) demodulator is demonstrated using a half-rate bang-bang phase detector commonly used in clock and data recovery (CDR) applications. This demodulator can be used for new home networking applications using already installed CATV lines. A prototype chip realized by 0.18-mum CMOS process can demodulate 622-Mb/s data at 1.4-GHz carrier frequency. At this data rate, the demodulator core consumes 27.5 mW from a 1.8 V power supply while the core chip area is 210 times 150 mum2. The transmission over 20-m CATV line using the prototype chip is successfully demonstrated.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:43 ,  Issue: 10 )