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A 6-bit 3.5-GS/s 0.9-V 98-mW Flash ADC in 90-nm CMOS

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5 Author(s)
Kazuaki Deguchi ; Adv. Analog Technol. Div., Renesas Technol. Corp., Itami ; Naoko Suwa ; Masao Ito ; Toshio Kumamoto
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A 6-bit 3.5-GS/s flash ADC is reported. A load circuit with a clamp diode and a replica-biasing scheme is developed for low-voltage and high-speed operation. An acceleration capacitor is introduced for high-speed overdrive recovery of a comparator. An averaging and interpolation network is employed in this ADC. The interpolation factor is optimized considering random offset, active area, and systematic offset to realize low offset and small active area. The ADC is fabricated in a 90-nm CMOS process and occupies 0.15 mm2. It consumes 98 mW with a 0.9-V power supply. With Nyquist input, SNDR and SFDR at 3.5 GS/s are 31.18 dB and 38.67 dB, respectively.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:43 ,  Issue: 10 )