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As feature size goes below 70 nm, process variation introduced device mismatch may cause over 40% performance variations and circuit failures especially for analog/mixed-signal designs. The location dependent correlations among devices and the large number of devices in some practical designs make it difficult to predict performance corners accurately and efficiently. This paper aims to provide an overview of possible methodologies and approaches that model and analyze device mismatch. In particular, the paper describes a new finite point device modeling technique that can speed up the analysis procedure, a new parametric reduction method and a novel Chebyshev Affine Arithmetic (CAA) based performance bound estimation approach.