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Parallel architecture for decoding LDPC Codes on high speed communication systems

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3 Author(s)
Morero, D.A. ; Digital Commun. Res. Lab., Nat. Univ. of Cordoba, Cordoba ; Corral-Briones, G. ; Hueda, M.R.

This paper presents a novel parallel architecture for decoding LDPC codes. The proposed architecture has low memory and interconnection requirements, becoming attractive for high speed applications such as fiber optic communications and high density magnetic recording. As an example, the implementation on an FPGA of a TPC/SPC code using the proposed architecture will also be described.

Published in:

Micro-Nanoelectronics, Technology and Applications, 2008. EAMTA 2008. Argentine School of

Date of Conference:

18-19 Sept. 2008

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