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Software implementation and performance analysis of the LTE physical layer blocks on a next generation baseband processor platform

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1 Author(s)
Babak D. Beheshti ; New York Institute of Technology, USA

Summary form only given. The Third Generation Partnership Project (3GPP) has been defining the Long Term Evolution (LTE) for 3G radio access. LTE has several areas of focus. These areas include enhancement of the Universal Terrestrial Radio Access (UTRA), as well as optimization of the network architecture with HSDPA (downlink) and HSUPA (uplink). LTE project aims to ensure the continued competitiveness of the 3GPP technologies for the future LTE focuses on download rates of 100 Mbit/s, upload rates of 50 Mbit/s per 20 MHz of bandwidth, increased spectrum efficiency and sub-5ms latency for small IP packets. This paper provides an overview of the radio interface physical layer requirements. The paper then presents the implementation of the current LTE standards on a second generation flexible baseband processor. The implementation will be be limited to the receiver chain blocks and will be entirely in ANSI C, written for a fixed point digital signal processors. The underlying assumption of this implementation is to avoid any hardware accelerators that would make the hardware platform for the baseband processing standard specific. The SB3500 is the second generation of SandBlaster-based low power, high performance system on a chip (SoC) products developed to serve the software defined radio (SDR) modem applications space. It is a multi-core device, containing 3 dasiaSBXpsila DSP cores. The software implementation of LTE physical layer includes implantation of OFDM and receiver chain processing in ANSI C. The projected processing requirements of an LTE UE on the SB3500 are presented with the expected number of cores needed for the data rates analyzed. The down-sampling filter used for the initial synchronization and for the fine synchronization, FFT block, Channel estimation for each reference symbol, MIMO detector and the CRC block are included in this analysis. The specific architectural features of the SB3500 and the compiler optimizations to yield a real time softw- - are implementation of LTE are also presented.

Published in:

Systems, Applications and Technology Conference, 2008 IEEE Long Island

Date of Conference:

2-2 May 2008