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Tapped delay lines are chain-like structures, which are able to measure short time intervals. Due to their homogeneous structure, they are particularly suited for being implemented on field-programmable gate arrays. But unfortunately, the attainable resolution in time is inherently limited to the average processing speed of the chainpsilas elements. As an alternative, this paper proposes a new architecture, called BOUNCE, in which all processing elements run in parallel. With its inherent parallelism, BOUNCE yields a resolution that depends on the variation, i.e., the differences, among the elementspsila processing speeds. The first prototype was implemented on an ALTERA StratixII 2S60 board Even though this board is clocked at only 85 MHz, the prototype yields a resolution of about 100ps.
Date of Conference: 15-18 Sept. 2008