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In future charged particle tracking systems, readout integrated circuits will be based on CMOS processes with minimum feature size in the 100 nm range. In nanoscale technologies, the reduction of the gate oxide thickness may lead to a non-negligible gate current due to direct tunneling phenomena. This leakage current, which is caused by discrete charges randomly crossing a potential barrier, yields an increase of the static power consumption for the digital section of the readout circuits and might degrade the noise performances of the analog front-end. As a consequence, in these advanced CMOS processes, an accurate characterization of the gate current noise is necessary in order to establish design criteria for detector analog front-end applications. This work presents the results of static and noise characterization of the gate-leakage current of NMOS devices belonging to a 90 nm commercial process. Data extracted from the measurements have been used to validate an analytical model for the gate current noise, which provides a useful tool for evaluating the impact of this noise source on the resolution limits achievable by low-noise charge amplifiers.