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An FPGA implementation of whitted-style ray tracing accelerator

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11 Author(s)
Woo-Chan Park ; Dept. of Comput. Eng., Sejong Univ., Seoul ; Jae-ho Nah ; Jeong-Soo Park ; Kyung-Ho Lee
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This paper presents an FPGA implementation of a full whitted-style ray tracing accelerator. It achieves about 1.3 M rays per second over realistic 3 D scenes. The future implementation with ASIC is expected to achieve real-time performance.

Published in:

Interactive Ray Tracing, 2008. RT 2008. IEEE Symposium on

Date of Conference:

9-10 Aug. 2008