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Considering layout for test scheduling of core-based SoCs

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2 Author(s)
Yu Xia ; Electr. & Comput. Eng., Portland State Univ., Portland, OR ; Chrzanowska-Jeske, M.

We consider a test-scheduling problem, with layout constraints, for core-based SOCs. Individual cores have to be tested on a system level after manufacturing and therefore special test access mechanisms (TAMs) are required. The amount of additional wires needed to route TAMs depends strongly on a SOC layout. In this research, we investigate the SOC test-scheduling problem formulated as the bin-packing problem and constrained by a physical layout of a SOC. We solve the problem using evolutionary strategy and sequence-pair representation. Our results, for ITC'02 benchmarks, show that for most examples, our algorithm generates solutions with less interconnects.

Published in:

Electronics, Circuits and Systems, 2005. ICECS 2005. 12th IEEE International Conference on

Date of Conference:

11-14 Dec. 2005