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Partitioning DSP applications to different granularity reconfigurable hardware

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3 Author(s)
M. D. Galanis ; VLSI Design Laboratory, Electrical and Computer Engineering Department, University of Patras, 26500, Greece ; G. Dimitroulakos ; C. E. Goutis

In this paper, we propose an automated partitioning methodology between the fine and coarse-grain reconfigurable hardware for improving performance. The fine-grain logic is implemented by an embedded FPGA unit, while for the coarse-grain reconfigurable hardware, a 2-dimensional array of processing elements is considered. These different granularity reconfigurable functional units are embedded in a hybrid platform. The proposed methodology mainly consists of three steps, the kernel identification, the mapping onto the coarse-grain reconfigurable array, and the mapping onto the fine-grain reconfigurable hardware. The experiments for five real-world applications show that the speedup, relative to an all-FPGA solution, ranges from 1.4 to 3.9 for the considered applications.

Published in:

Electronics, Circuits and Systems, 2005. ICECS 2005. 12th IEEE International Conference on

Date of Conference:

11-14 Dec. 2005