By Topic

VHDL-AMS modeling of a multi-standard phase locked loop

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)

The aim of this study is to provide a high-level VHDL-AMS model for multi-standard phase locked loop in SOI technology. The supported standards are GSM, GPS, DCS, Bluetooth, Wifi and WLAN. The model can be used to evaluate settling times, channel-to-channel transition times and also the timing needed to switch from one standard to another one. VCO noise, propagation time, transistors mismatch and slew rate and filter corner models are taken into account and their influences are evaluated.

Published in:

Electronics, Circuits and Systems, 2005. ICECS 2005. 12th IEEE International Conference on

Date of Conference:

11-14 Dec. 2005