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A 60 GHz single-chip CMOS radio has been fully integrated using standard 90 nm CMOS process technology. The digitally controlled wideband super-heterodyne architecture combined with a high-speed digital signal processor has been designed to support the whole 57 to 66 GHz bandwidth available, and enable data throughput exceeding 7Gbps QPSK and 15 Gbps 16 QAM for a total DC power budget below 200 mW. The receiver chain provides a total gain of nearly 50 dB for a total noise figure below 9 dB while the power amplifier delivers +8.4 dBm saturated output power at 60 GHz. The single-chip radio is digitally controlled via a standard SPI, and scalable to a phased array architecture. This is the highest level of integration for a 60 GHz single-chip transceiver reported till date. The design has been optimized for robustness against process variation and temperature, and verified by measurement results.