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MVBLA based design of Constrained 1-bit Transform based motion estimation algorithm

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5 Author(s)

In this work a novel hardware proposed for Constrained 1-bit Transform based motion estimation to facilitate real time operation. The designed system occupies a small area in a general purpose FPGA fabric and it is therefore efficient to implement a whole video coding architecture on a single FPGA chip. The designed system can perform ME operation for a 2048times1152 pixel sized image frame at a speed of 20 frames/second.

Published in:

Signal Processing, Communication and Applications Conference, 2008. SIU 2008. IEEE 16th

Date of Conference:

20-22 April 2008