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Effects of Parasitic Capacitance, External Resistance, and Local Stress on the RF Performance of the Transistors Fabricated by Standard 65-nm CMOS Technologies

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10 Author(s)

Effects of parasitic capacitance, external resistance, and local stress on the radio-frequency (RF) performance of the transistors fabricated by 65-nm CMOS technology have been investigated. The effect of parasitic capacitance, particularly Cgb, becomes significant due to the reduced spacing between the gate and the substrate contact (SC) in proportion to scaling down. Current drivability (Idsat) per unit width has been improved through introduction of mobility enhancement techniques. The influence of external resistance becomes more pronounced for large-dimensional RF transistors due to severe IR drop. Such improved current drivability and large external resistance is responsible for dc performance (gm) degradation and, eventually, cutoff frequency (fT) degradation. Local stress effects associated with silicon nitride capping layer and STI stress have been investigated. fT is largely affected by local stress change, i.e., gm degradation at minimal gate poly (GP) pitch and gate-to-active spacing, fT is dominated by increased parasitic capacitance (Cgb) with increasing GP pitch and gate-to-active spacing. Above 10% improvement in fT has been observed through layout optimization for Cgb reduction by increasing the transistor active-to-SC spacing.

Published in:

Electron Devices, IEEE Transactions on  (Volume:55 ,  Issue: 10 )

Date of Publication:

Oct. 2008

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