By Topic

Gate Influence on the Layout Sensitivity of  \hbox {Si}_{1 - x}\hbox {Ge}_{x} \hbox {S/D} and \hbox {Si}_{1 - y}\hbox {C}_{y} \hbox {S/D} Transistors Including an Analytical Model

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)

We present a simulation study on the effect of the gate module on the channel stress in Si1-xGex and Si1-yCy S/D MOS transistors. Stiff gate materials, such as titanium nitride, lead to a decreased channel stress, while a replacement-gate scheme allows the increase of the effectiveness of the Si1-xGex and Si1-yCy S/D techniques significantly, independent of the gate material used. The drawback of using a replacement gate is that the channel stress becomes more sensitive to layout variations. In terms of effect on Si1-xGex/Si1-yCy S/D stress generation, using a thin metal gate capped by polysilicon is similar to a full metal gate if the thin metal gate thickness exceeds 10 nm. Even metal gates as thin as 1 nm have a clear influence on the stress generation by Si1-xGex/Si1-yCy S/D. Removing and redepositing the polysilicon layer while leaving the underlying metal gate unchanged increases the stress, although not to the same extent as for complete gate removal. A simple analytical model that estimates the stress in nested short-channel Si1-xGex and Si1-yCy S/D transistors is presented. This model includes the effect of germanium/carbon concentration, active-area length, as well as the effect of gate length and the Young's modulus of the gate. Good qualitative agreement with 2-D finite element modeling is demonstrated.

Published in:

Electron Devices, IEEE Transactions on  (Volume:55 ,  Issue: 10 )