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Implementation of matrix-type FDTD algorithm on a graphics accelerator

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4 Author(s)
Dziekonski, A. ; Dept. of Microwave & Antenna Eng., Gdansk Univ. of Technol., Gdansk ; Sypek, P. ; Kulas, L. ; Mrozowski, M.

This paper presents initial conclusions concerning the implementation of matrix-type FDTD algorithm on a low cost graphics accelerator (Nvidia GeForce GT 512 MB, 1.188 GHz) in CUDA (compute unified device architecture). Authors of this article pose a question as to whether using the graphics accelerator based on SIMD architecture (single instruction, multiple data) is reasonable in programming a matrix-type FDTD algorithm, then results of tests meant to compare the efficiency of sequential and parallel implementation are presented.

Published in:
Microwaves, Radar and Wireless Communications, 2008. MIKON 2008. 17th International Conference on

Date of Conference: 19-21 May 2008

Page(s):
1 - 4
Print ISBN:
978-83-906662-8-0
INSPEC Accession Number:
10221627
Conference Location :
Wroclaw
Product Type:
Conference Publications

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