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Classical connected components labelling algorithms are unsuitable for real-time processing of streamed images on an FPGA because they require two passes through the image. The basic requirements of connected components analysis are investigated, and this led to a novel single-pass approach that avoids the need to buffer an intermediate image. This is further analysed to give an algorithm that is both memory efficient and has the minimum latency. The final algorithm reduces the memory by over 300 times, and reduces the latency by more than a factor of 2.