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Recent generation of FPGA devices takes advantage of speed and density benefits resulted from heterogeneous FPGA architecture, in which several basic LUTs can be combined to form one larger size LUT called macro. Large macros not only decrease network depth efficiently but also reduce area. In this paper, a new technology mapping algorithm, named MacroMap is proposed for the heterogeneous FPGAs with effective area estimation to overcome the main disadvantage that traditional technology mapping algorithms only generate one kind of typical K-LUT and cannot make full use of LUTs with different sizes (basic LUTs and macros). Experimental results show that MacroMap can obtain 19% gain on area while keeping the network depth optimal compared with the existing heterogeneous FPGA mapping algorithm heteromap.