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Performance optimization by track swapping on critical paths utilizing random variations for FPGAS

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4 Author(s)
Sugihara, Y. ; Dept. of Commun. & Comput. Eng., Kyoto Univ., Kyoto ; Kume, Y. ; Kobayashi, K. ; Onodera, H.

Since FPGAs in future deep sub-micron processes will suffer from drastic speed and yield losses caused by device variations, we propose variation-aware reconfiguration that utilizes these variations for performance enhancement. To utilize random variations on a current deep submicron process for performance enhancement, optimizing each device from a common configuration is better than producing optimized configurations based on detailed measurement results. In this paper we apply a track swapping procedure to critical path reconfiguration. First, we configure all fabricated FPGAs with common configuration data. The configuration of each die is optimized to reroute the critical paths that do not satisfy timing specifications. The rerouting of a critical path usually causes serious topology changes that may prolong other paths and create new critical paths. In the track swapping procedure, we swap a wire track on a critical path for the adjacent track without any topology changes by switching blocks with more flexibility. We experiment on performance enhancement by applying track swapping to LGSynth93 benchmark circuits. The average speed enhancement is 2.45%, and the average yield enhancement is 32.7% when the standard deviation of the random variations is 10.0%.

Published in:

Field Programmable Logic and Applications, 2008. FPL 2008. International Conference on

Date of Conference:

8-10 Sept. 2008