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Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory

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6 Author(s)
Meikang Qiu ; Dept. of Electr. Eng., Univ. of New Orleans, New Orleans, LA ; Jiande Wu ; Xue, C.J. ; Jingtong Aaron Hu
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Many high-performance DSP processors employ multi-bank on-chip memory to improve performance and energy consumption. This architectural feature supports higher memory bandwidth by allowing multiple data memory accesses to be executed in parallel. This paper studies the scheduling and assignment problem on minimizing the total energy consumption while satisfying timing constraint with heterogeneous multi-bank memory for applications with loop. An algorithm, TASL (Type Assignment and Scheduling for Loops), is proposed. The algorithm uses loop scheduling and assignment with the consideration of variable partition to find the best configuration for both memory and ALU.

Published in:

Field Programmable Logic and Applications, 2008. FPL 2008. International Conference on

Date of Conference:

8-10 Sept. 2008