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Instruction buffer mode for multi-context Dynamically Reconfigurable Processors

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5 Author(s)
Toru Sano ; Department of Information & Computer Science, Keio University, 3-14-1 Hiyoshi, Kohokuk-ku, Yokohama, 223-8522 Japan ; Masaru Kato ; Satoshi Tsutsumi ; Yohei Hasegawa
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In multi-context dynamically reconfigurable processor array (DRPA), the required number of contexts is often increased by those with low resource usage. In order to execute such contexts without wasting a context memory, we propose a new execution mode called instruction buffer mode in addition to the normal multi-context mode. In this mode, a configuration code from the central configuration memory is stored in the instruction buffer and executed directly. Furthermore, by exploiting a multicast method, a single configuration code loaded to the buffer can be executed by multiple processing elements in a SIMD fashion. We also investigate a mode selection policy based on simple formulas. From the result of implementation and evaluation by using a prototype DRPA called MuCCRA-1, it appears that the total execution time is reduced 12% by using the instruction buffer mode, while 12% of the semiconductor area is increased.

Published in:

2008 International Conference on Field Programmable Logic and Applications

Date of Conference:

8-10 Sept. 2008