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FPGA implementation of a flexible decoder for long LDPC codes

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2 Author(s)
Beuschel, C. ; Inst. of Microelectron., Univ. of Ulm, Ulm ; Pfleiderer, Hans-Jörg

Over the last years LDPC codes became more and more popular because of their near Shannon limit error correcting performance. Structured code classes which ease decoder design have already been standardized for DVB-S2, IEEE WiMax 802.16e or WiFi. In this paper we introduce a flexible decoder architecture which can decode any structured or unstructured LDPC code using the identical hardware. Furthermore we present a mapping algorithm which ldquocompilesrdquo the parity-check matrix of the desired LDPC code. This concept allows adaption of the decoder controller to different LDPC codes without requiring a new synthesis run. We implemented the proposed decoder on a XILINX XC4LX160 FPGA and give bit error rates to verify design and mapping algorithm. In contrast to previously presented flexible implementations our design is able to decode LDPC codes of 30 times longer codeword lengths up toN = 65, 000.

Published in:

Field Programmable Logic and Applications, 2008. FPL 2008. International Conference on

Date of Conference:

8-10 Sept. 2008