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NOC architecture design for multi-cluster chips

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3 Author(s)
Henrique C. Freitas ; Informatics Institute, Universidade Federal do Rio Grande do Sul Porto Alegre, RS, Brazil ; Philippe O. A. Navaux ; Tatiana G. S. Santos

For the next generation of multi-core processors, the on-chip interconnection networks must be efficient to achieve high data throughput and performance. Moreover, these interconnections must be flexible and scalable in order to provide parallel on-demand computing. For this reason, the goal of this paper is to present design decisions of a multi-cluster NoC (MCNoC) architecture in order to support collective communication patterns through topology reconfiguration on an FPGA-based multi-cluster chip. The MCNoCpsilas results show a small area occupation, low power consumption and high performance.

Published in:

2008 International Conference on Field Programmable Logic and Applications

Date of Conference:

8-10 Sept. 2008