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A New Family of Sequential Elements With Built-in Soft Error Tolerance for Dual-VDD Systems

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3 Author(s)
Saihua Lin ; Electron. Eng. Dept., Tsinghua Univ., Beijing ; Huazhong Yang ; Rong Luo

In this paper, we propose some soft-error-tolerant latches and flip-flops that can be used in dual-VDD systems. By utilizing local redundancy and inner feedback techniques, the latches and flip-flops can recover from soft errors caused by cosmic rays and particle strikes. The proposed flip-flop can be used as a level shifter without the problems of static leakage and redundant switching activity. Implemented in a standard 0.18- mum technology, the proposed latches and flip-flops show superior performance compared to conventional ones in terms of delay and power while keeping the soft-error-tolerant characteristic. Experimental results show that compared to the traditional built-in soft-error-tolerant D latch, the D-QN delay of the new D latch is 29.1% less than that of the traditional built-in soft-error-tolerant D latch while consuming 16.5% less power as well. The D-Q delay and power of the new flip-flop are about 47.7% and 54% less than those of the traditional high speed level-converting flip-flop, respectively. In addition, the proposed flip-flop is more robust to soft errors. The critical charge which represents the minimum charge at the D input required to cause an error of the flip-flop can be increased by more than 46.4%. The time window during which the flip-flop will be erroneous caused by single-event upsets at the D input is reduced by more than 22.2%.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:16 ,  Issue: 10 )

Date of Publication:

Oct. 2008

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