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Optimal robust compression of test responses

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2 Author(s)
Karpovsky, M.G. ; Dept. of Electr. Comput. & Syst. Eng., Boston Univ., MA, USA ; Nagvajara, P.

A compression of test responses technique for a built-in self-test (BIST) VLSI design is presented. The authors introduce the notion of a robust compression technique which incorporates prior knowledge of the statistics of fault-free responses under pseudorandom testing to achieve a guaranteed error detectability independent of a distribution of errors. The presented robust quadratic compressor requires two r-bit registers (r-bit signature) more than a multiple-input linear feedback shift register; however, it provides for equal protection against all error patterns. Therefore, quadratic compressors are optimal and robust with respect to a statistics of errors in a device under test

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Computers, IEEE Transactions on  (Volume:39 ,  Issue: 1 )