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Design and analysis of a gracefully degrading interleaved memory system

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4 Author(s)
Cheung, K.C. ; Digital Equipment Corp., Hong Kong ; Sohi, G.S. ; Salvia, K.K. ; Pradhan, D.K.

The organization of interleaved memories in such a way that faults in the memory system degrade the performance in a graceful manner is studied. Attention is restricted to an interleaved memory system that starts out with 2q memory banks and uses a low-order interleaving scheme. The motivation and design objectives of the memory system are described. A new reconfiguration scheme and the design of the hardware needed to implement it are presented. The reconfiguration scheme is evaluated using trace-driven simulation for a number of benchmarks. The ideas presented can easily be extended to other interleaved memory schemes

Published in:

Computers, IEEE Transactions on  (Volume:39 ,  Issue: 1 )

Date of Publication:

Jan 1990

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