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Variations in supply (V dd) and threshold voltages (V th) significantly impact parametric yield. These variations also affect V dd and V th scaling, two power reduction techniques that effectively reduce dynamic and static power consumption. This paper presents a statistical methodology for maximizing yield and optimizing supply and threshold voltage scaling under the V dd and V th variations. A design-specific feasible region is constrained by a minimum performance and maximum temperature in the V th - V dd plane. A tolerance box is placed in the feasible region so that its center provides the nominal values for V dd and V th such that the design has a maximum immunity to the variations and maximizes the yield for the given constraints. It is demonstrated that the location of the tolerance box and, therefore, the values of V dd and V th depend on the design metrics, circuit switching activity, transistor sizing, and the given constraints. Monte Carlo simulations indicate a 25% increase in the yield for 90-nm CMOS technology. In addition, the methodology can be adopted as a variability-aware guideline in a design specific power and performance optimization and is applicable to both continuous and discrete voltage scaling. SPECTRE simulations verify the developed method.