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Charge Recycling in Power-Gated CMOS Circuits

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3 Author(s)
Ehsan Pakbaznia ; Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA ; Farzan Fallah ; Massoud Pedram

The design of a suitable power gating (e.g., multithreshold or super cutoff CMOS) structure is an important and challenging task in sub-90-nm very large scale integration (VLSI) circuits where leakage currents are significant. In designs where the mode transitions are frequent, a significant amount of energy is consumed to turn on or off the power gating structure. It is thus desirable to develop a power gating solution that minimizes the energy consumed during mode transitions. This paper presents such a solution by recycling charge between the virtual power and ground rails immediately after entering the sleep mode and just before wakeup. The proposed method can save up to 43% of the dynamic energy wasted during mode transition while maintaining the wakeup time of the original circuit. It also reduces the peak negative voltage value and the settling time of the ground bounce.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:27 ,  Issue: 10 )