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FPGA Implementation of the SMS4 Block Cipher in the Chinese WAPI Standard

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4 Author(s)
Xianwei Gao ; Beijing Electron. Sci. & Technol. Inst., Beijing ; Erhong Lu ; Liqin Xian ; Hanlin Chen

SMS4 is a 32-round block cipher with a 128-bit block size and a 128-bit user key. This paper presents rolling and unrolling field programmable gate array implementation of the SMS4 algorithm, and both the encryption and the decryption algorithms of SMS4 have been implemented on the same FPGA. The rolling design of SMS4 for area requires 1552 ALMs, the maximum operating clock is 139MHz and the corresponding data throughput is about 539 Mbit/s. The unrolling design of SMS4 for speed requires 8373 ALMs, the maximum operating clock is 162 MHz and the corresponding data throughput is about 20736 Mbit/s. Our SMS4 implementation has a good balance between high performance and low complexity in area as a result of taking advantage of certain features present in Straitx II FPGA and some design strategies.

Published in:

Embedded Software and Systems Symposia, 2008. ICESS Symposia '08. International Conference on

Date of Conference:

29-31 July 2008