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On-Chip Memory System Optimization Design for the FT64 Scientific Stream Accelerator

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10 Author(s)
Mei Wen ; Nat. Univ. of Defense Technol., Beijing ; Nan Wu ; Chunyuan Zhang ; Qianming Yang
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In this paper shows the extension of application domains, hardware-managed memory structures such as caches are drawing attention for dealing with irregular stream applications. However, since a real application usually has both regular and irregular stream characteristics, conventional stream register files, caches, or combinations thereof have shortcomings. This article focuses on combining software- and hardware-managed memory structures and presents a new syncretic memory system based on the ft64 stream accelerator.

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Micro, IEEE  (Volume:28 ,  Issue: 4 )