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A 2-port SRAM cell has to guarantee stability against simultaneously read and write (R/W)-disturbed accesses while keeping cell current (Icell). We verified that it was difficult to provide the stability without any decrease in Icell and any increase in the cell-area penalty only by using the previously proposed techniques for a 1-port cell, and have proposed a new cell biasing technique that controlled the level of the cell VSS (VSSM) with a dual-Vdd and a reduced write-bit-line (WBL) precharge scheme for an 8-transistor (8T) 2-port cell to address the above issue. In this paper, a further consideration was newly demonstrated about the stability for a 2-port SRAM under the random fluctuation of the threshold-voltage (Vth) in 65-nm CMOS technology. The stability with the proposed biasing was compared with that of the conventional cell-Vdd (VDDM) control for write assist. The results under 4-sigma random-Vth fluctuation verified that the minimum Icell at a simultaneously R/W-disturbed cell increased by 2.4 times at Vdd=0.9 V while improving the write margin (WRTM). The cell size based on the same Icell was reduced by 20%. The minimum static noise margin (SNM) was also improved by 44%. Each stability also had the tolerance against 6-sigma random-Vth fluctuation. Furthermore, we have challenged to apply the proposed cell biasing to a 7-transistor (7T) 2-port cell design for area saving with a unique write-assist scheme. The cell size was reduced by 26% with the 7T cell compared with that of the conventional 8T cell. This proposed cell biasing satisfied all the requirements of 2-port SRAM operation while improving stability and saving cell size.
Date of Publication: Sept. 2008