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An 8.6 mW 25 Mvertices/s 400-MFLOPS 800-MOPS 8.91 mm ^{2} Multimedia Stream Processor Core for Mobile Applications

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4 Author(s)
Shao-Yi Chien ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei ; You-Ming Tsao ; Chin-Hsiang Chang ; Yu-Cheng Lin

For the demands of mobile multimedia applications, a stream processor core is designed with 8.91 mm2 area in 0.18 mum CMOS technology at 50 MHz. Several techniques and architectures are proposed to achieve high performance with low power consumption. First of all, an optimized core pipeline is designed with 2-issue VLIW architecture to achieve the processing capability of 400 MFLOPS or 800 MOPS. In addition, adaptive multi-thread scheme can increase the performance by increasing hardware utilization, and the proposed configurable memory array architecture can reduce off-chip memory accessing frequency by caching both input data and output results. Furthermore, for graphics applications, a geometry-content-aware technique called early-rejection-after-transformation is proposed to remove redundant operations for invisible triangles. As for video applications, the proposed video accelerating instruction set can support motion estimation for video coding. Experimental results show that 86% power reduction and more than ten times speedup of the VLIW architecture can be achieved with the proposed techniques to provide the processing speed of 25 Mvertices/s and power consumption of 8.6 mW. Moreover, CIF (352 times 288) 30 fps video encoding with the search range of {H[-24,24], V[-16,16]} is also supported by the proposed stream processor. By supporting both video and graphics functions, this highly efficient, high performance, and low power processor core is applicable to multimedia mobile devices.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:43 ,  Issue: 9 )