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Improving the Performance of Multithreaded Sparse Matrix-Vector Multiplication Using Index and Value Compression

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3 Author(s)
Kourtis, K. ; Sch. of Electr. & Comput. Eng., Nat. Tech. Univ. of Athens, Athens ; Goumas, G. ; Koziris, N.

The sparse matrix-vector multiplication kernel exhibits limited potential for taking advantage of modern shared memory architectures due to its large memory bandwidth requirements. To decrease memory contention and improve the performance of the kernel we propose two compression schemes. The first, called CSR-DU, targets the reduction of the matrix structural data by applying coarse grain delta encoding for the column indices. The second scheme, called CSR-VI, targets the reduction of the numerical values using indirect indexing and can only be applied to matrices which contain a small number of unique values. Evaluation of both methods on a rich matrix set showed that they can significantly improve the performance of the multithreaded version of the kernel and achieve good scalability for large matrices.

Published in:

Parallel Processing, 2008. ICPP '08. 37th International Conference on

Date of Conference:

9-12 Sept. 2008