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Analyzing the impact of data prefetching on Chip MultiProcessors

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4 Author(s)
Fukumoto, N. ; Dept. of Inf., Kyushu Univ., Fukuoka ; Mihara, T. ; Inoue, K. ; Murakami, K.

Data prefetching is a well known approach to compensating for poor memory performance, and has been employed in commercial processor chips. Although a number of prefetching techniques have so far been proposed, in many cases, they have assumed single-core architectures. In chip multiprocessor (or CMP) chips, there are some shared resources such as L2 caches, buses, and so on. Therefore, the effect of prefetching on CMP should be different from traditional single-core processors. In this paper, we analyze the effect of prefetching on CMP performance. This paper first classifies the impact of prefetches issued during program execution. Then, we discuss quantitatively the effect of prefetching to memory performance. The experimental results show that the negative effect of invalidation of prefetched cache blocks is very small. In addition, it is observed that the current prefetch algorithms do not exploit effectively the feature of CMPs, i.e. cache-to-cache on-chip data transfer.

Published in:

Computer Systems Architecture Conference, 2008. ACSAC 2008. 13th Asia-Pacific

Date of Conference:

4-6 Aug. 2008