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We propose a UML-based hardware/software co-design platform for partially reconfigurable systems, targeting mainly at network security systems. Applications with heavy computing are implemented as the partially reconfigurable hardware tasks for enhancing the system performance and flexibility, which means that a network security embedded system can dynamically reconfigure one part of the system at run-time according to different security needs while other parts are still functioning. We further propose a partially reconfigurable hardware template, using which the users only need to integrate their hardware applications with the template without going through the full partial reconfiguration flow. The template has an average overhead of only 0:62% of the total resources in Xilinx Virtex-II XC2V3000 FPGA. Furthermore, our proposed platform includes a UML-based system model that can directly interact with the system hardware architecture. Compared to the synthesis based estimation methods with inaccuracy ranging from -23% to +234% for the execution time of dynamically partially reconfigurable hardware tasks, by using our platform users can directly measure the execution time and use them to validate system correctness and performance at a high-level phase, which significantly reduces the number of iterations in the system development.