Skip to Main Content
A CMOS radio frequency (RF) polar transmitter architecture for a UHF (860-960 MHz) RF identification (RFID) reader is proposed, which consists of a switch-mode CMOS power amplifier (PA) and an analog pulse-shaping filter implemented in 0.25-mum CMOS process. The amplitude modulation of a amplitude shift keying signal is performed by simply switching the common gate transistor of a cascode power amplifier. Extremely low power consumption is achieved when the PA is switched off. The power efficiency of the transmitter is enhanced not only by using switching power amplifier but also by employing this architecture.
Date of Publication: Sept. 2008