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A CMOS Harmonic Rejection Mixer With Mismatch Calibration Circuitry for Digital TV Tuner Applications

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4 Author(s)
Hyouk-Kyu Cha ; Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon ; Seong-Sik Song ; Hong-Teuk Kim ; Kwyro Lee

A harmonic rejection mixer with mismatch calibration circuitry in direct-conversion receiver architecture for digital TV tuner applications is designed and fabricated in 0.18-mum CMOS technology. Odd harmonic mixing in the 48-862 MHz digital TV frequency band between the input signal and the local oscillator harmonics is a critical problem for direct-conversion receivers which require a harmonic rejection of over -60 dBc for ATSC terrestrial and cable digital TV standards. Without calibration, harmonic rejection mixers show a rejection ratio of the third and fifth harmonics in the range of -30 to -40 dBc due to phase and/or gain mismatch. The implemented harmonic rejection mixer with the proposed calibration circuitry consistently achieves more than -70 dBc of third harmonic rejection without degrading other performances such as gain, noise figure, linearity, and power consumption.

Published in:

Microwave and Wireless Components Letters, IEEE  (Volume:18 ,  Issue: 9 )